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In reg - mem architecture, clock cycle is 10 ns wide. It is proposed that reg - reg architecture be used instead, that reduces the clock cycle by 2 ns. However, it requires an additional load instruction, in some cases! Will the new processor be more efficient, if so under what circumstances? Quantify your answer.


In reg-mem architecture, clock cycle is 10 ns wide. It is proposed that reg-reg architecture be used instead, that reduces the clock cycle by 2 ns. However, it requires an additional load instruction, in some cases! Will the new processor be more efficient, if so under what circumstances? Quantify your answer.

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