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A computer architect is designing a hardware datapath implementation and the architect has determined following circuit element delays. Instruction Memory 150 ps Decode 70 ps Register Fetch 60 ps ALU 150 ps Data Memory 200 ps Register Write Back 60 ps (a) What is the length of a clock cycle for a single cycle datapath implementation? (b) What would be the frequency of a processor, corresponding to single datapath implementation? (c) What would be the length of fastest clock cycle for a 5 - stage pipeline datapath? What would be the corresponding processor frequency? (d) How much faster is the 5 - stage pipelined datapath compared to the single cycle datapath implementation?


A computer architect is designing a hardware datapath implementation and the architect has determined following circuit element delays.


Instruction Memory       150 ps


Decode                           70 ps


Register Fetch                60 ps


ALU                               150 ps


Data Memory                200 ps


Register Write Back       60 ps


(a) What is the length of a clock cycle for a single cycle datapath implementation?


(b) What would be the frequency of a processor, corresponding to single datapath implementation?


(c) What would be the length of fastest clock cycle for a 5-stage pipeline datapath? What would be the corresponding processor frequency?


(d) How much faster is the 5-stage pipelined datapath compared to the single cycle datapath implementation?

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1 Answers

Salahudin Khan
13 Points
3 years ago
(a) What is the length of a clock cycle for a single cycle datapath implementation? Solution: Time(lw) = Time(IF) + Time(ID+Reg.File) + Time(ALU) + Time(MemRead) Time(lw) = 150 + (70+60) + 200 + 60 Time(lw) = 690ps (b) What would be the frequency of a processor, corresponding to single datapath implementation? Solution: As we know Frequency =The value of clock cycle for single cycle is 1. It means that frequency of processor corresponding to single cycle datapath is 1. Frequency can be defined as Frequency = 1/clock rate+ Time(Reg.FileWrite)1GHz c. where c is the maximum clock cycle. =1/690* 10^-12*10^9 =1/690*10^ -3=1000/690= 1.44 9GHz=1.45GHz (c) What would be the length of fastest clock cycle for a 5-stage pipeline datapath? What would be the corresponding processor frequency? Solution: Fastest clock cycle is that whose latency is minimum i.e 60 ps. but when we calculate the frequency, we have to consider the slowest cycle length in multi-cycle datapath that is 200 ps. So , Frequency = 1200 ps 1 -12 9 -3 *10 *10 =1/200*10 =1000/200=5 GHz (d) How much faster is the 5-stage pipelined datapath compared to the single cycle datapath implementation? Single cycle execution time= 690 ps Execution time for multi cycle = 200ps So 690/200ps=3.45 times faster It means that 5-stage pipelined datapath is 3.45 time faster than single cycle datapath. If we analyze this according to frequency point of view then 5GHz/1.45GHz=3.45 times faster

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