A computer architect is designing a hardware datapath implementation and the architect has determined following circuit element delays.
Instruction Memory 150 ps
Decode 70 ps
Register Fetch 60 ps
ALU 150 ps
Data Memory 200 ps
Register Write Back 60 ps
(a) What is the length of a clock cycle for a single cycle datapath implementation?
(b) What would be the frequency of a processor, corresponding to single datapath implementation?
(c) What would be the length of fastest clock cycle for a 5-stage pipeline datapath? What would be the corresponding processor frequency?
(d) How much faster is the 5-stage pipelined datapath compared to the single cycle datapath implementation?
A computer architect is designing a hardware datapath implementation and the architect has determined following circuit element delays.
Instruction Memory 150 ps
Decode 70 ps
Register Fetch 60 ps
ALU 150 ps
Data Memory 200 ps
Register Write Back 60 ps
(a) What is the length of a clock cycle for a single cycle datapath implementation?
(b) What would be the frequency of a processor, corresponding to single datapath implementation?
(c) What would be the length of fastest clock cycle for a 5-stage pipeline datapath? What would be the corresponding processor frequency?
(d) How much faster is the 5-stage pipelined datapath compared to the single cycle datapath implementation?










