How to design circuit diagram of cmos ring oscillator?

							Aring oscillatoris a device composed of an odd number ofNOT gateswhose outputoscillatesbetween two voltage levels, representingtrueandfalse. The NOT gates, or inverters, are attached in a chain; the output of the last inverter is fed back into the first.
CMOS Ring Oscillator (RO) is an integral part of phase locked loops (PLL).The increasing demand for bandwidth, places stringent requirements on the spectral purity of oscillators..These oscillators due to their integral nature are used in many applications such as integral frequency synthesis, clock and data recovery in communication systems and on chip clock distribution . The design of an efficient RO circuit operating at radio frequencies with optimal performance is quite challenging for an RFIC designer. The performance of a RO is characterized by a number of performance measures such as operating frequency, figure of merit, tuning range and area. These performance indices are guiding measures for designers to size the transistors and bias the circuit. In the semiconductor industry an analog IC designer puts lots of manual efforts to perform circuit sizing for a particular circuit to meet the required specifications.